IARPA releases SuperTools BAA

On June 7, the Intelligence Advanced Research Projects Activity (IARPA) released a broad agency announcement for SuperTools (IARPA-BAA-16-03). The proposal due date for initial round of selections is 5:00 pm Eastern Time on August 1, 2016. The BAA’s closing date is June 8, 2017.

SuperTools seeks to develop a superconducting circuit design flow with a comprehensive set of Electronic Design Automation (EDA) and Technology Computer Aided Design (TCAD) tools for Very-Large-Scale Integration (VLSI) design of Superconducting Electronics (SCE).

The Intelligence Community (IC) is well known to be a major consumer of high performance computing, but is increasingly finding itself frustrated by limitations in overall power consumption and clock speed. The amazing successes of semiconductor technology embodied in Moore’s Law give the impression that computing power might continue on its exponential growth curve indefinitely. However there are limits of miniaturization and switching speeds imposed by physics as applied to semiconductors, and these limits are now being felt. Clock speeds are starting to stagnate, and device features are now only a few tens of atoms in size, and so the search for alternative high speed and low power technologies must move on to more exotic materials and design concepts.

Superconducting Electronics (SCE) offers a promising alternative to complementary metal-oxide semiconductor (CMOS) technology. However, as with many disruptive technologies, in order to displace the reigning champion, there is a lot of ground to make up. New pulse-based logic families operating at very low power levels are starting to be developed, but if they are to compete with semiconductors, they will have to show performance advantages for highly complex circuits. The semiconductor industry has had the advantage of decades of development of ever more sophisticated design tools that keep creating ever more sophisticated circuits. 6 The state of SCE design tools lags far behind that of CMOS design tools. Fortunately, there are many lessons learned in the CMOS world that can be directly applied to the SCE world. However there are also several features of SCE that have no direct analog and any suite of SCE design tools will have to accommodate those differences. It is to be expected that some of the current CMOS design tools can be applied with only small changes to the SCE design problem. Other design tools may require major changes or completely innovative approaches.

The overarching goal of the SuperTools program is the creation of a full suite of design tools that will facilitate the design of an SCE central processing unit (CPU) as well as other complex SCE circuits. The art of digital design for SCE has seen very simple handcrafted circuits run with clock speeds in excess of 500 GHz. However, even modestly sized handcrafted circuits sometimes fail to work at all. Whether very fast and low power complex SCE circuits can be designed with suitable modified Computer Aided Design (CAD) tools is the challenge that the SuperTools program must address.

IARPA’s SuperTools program is closely coordinated with other IARPA programs in SCE, and in particular with the C3 program. It is expected that software developed for the SuperTools program will be made available to the C3 program for use in that program’s Logic Design thrust.

Full information is available here.

Source: FedBizOpps