Galois awarded $4.5M DARPA contract to strengthen hardware security
On January 24, Portland, OR-based Galois announced that it has been awarded a multi-year contract by the Defense Advanced Research Projects Agency (DARPA) Microsystems Technology Office (MTO) to develop tools and methodologies that enable provable security for hardware used in a broad range of consumer, business, and government products. Phase I of the award will amount up to $4.5 million, dependent on successful completion of milestones.
The Galois-led project falls under the DARPA MTO System Security Integrated through Hardware and Firmware (SSITH) program. The goal of SSITH is to develop hardware design tools that provide security against hardware vulnerabilities that are exploited through software in DoD and commercial electronic systems.
To measure the effectiveness of such hardware security protection, Galois’s BESSPIN (Balancing Evaluation of System Security Properties with Industrial Needs) project aims to develop a set of security metrics, a framework for expressing and reasoning about hardware security, and a methodology in which metrics drive decision making during the design of secure systems.
“While there is so much focus today on developing secure software, even the most hardened software becomes flawed if wrapped around vulnerable hardware,” said Joe Kiniry, principal scientist, Galois. “BESSPIN aims to re-imagine traditional security approaches so that organizations can make evidence-based hardware and firmware design trade-offs between security and other characteristics such as performance, power, and area.”
BESSPIN seeks to generates powerful new hardware security assurance capabilities for CPU and semiconductor vendors, hardware manufacturers, and the DoD. For example, a company might state that they have thought hard about memory errors such as buffer overflow, and that their new hardware architecture has been designed to prevent them. BESSPIN aims to enable the objective evaluation of that claim against the company’s actual product.
DARPA MTO is focused on creating and preventing strategic surprise through investments in compact microelectronic components such as microprocessors, microelectromechanical systems (MEMS), and photonic devices.
The team selected for this project, which includes Galois and partners Bluespec and Reduced Energy Microsystems (REM), includes experts in formal methods, programming and hardware design languages, hardware design and EDA tooling, and system architecture.
As a part of the SSITH program, it is the goal of the BESSPIN team to reason about the correctness and security of three different RISC-V secure CPUs from up to eight different SSITH teams through three releases—potentially adding up to 72 CPUs in all. These CPUs would use a wide variety of techniques to ensure system security, and aim to be written in multiple hardware design languages including System Verilog, Bluespec, and Chisel. The BESSPIN tools that Galois develops must accommodate this enormous range of techniques and technologies.