IARPA releases RFI for Electronic Design Automation tools for Superconducting Electronics (EDA for SCE)

The Intelligence Advanced Research Projects Activity (IARPA) seeks information on the availability and development of electronic design automation (EDA) tools for superconducting electronics (SCE). Interested contractors should note that the deadline for responses is 4:00pm EST February 13, 2015.

 To reach its goal of building a prototype superconducting computer, IARPA’s Cryogenic Computing Complexity (C3) program will need to produce superconducting circuits of unprecedented density and complexity [1, 2]. The C3 program will be fabricating circuits using the 10-metal layer, fully planarized process at Lincoln Laboratory [3, 4]. The sophistication of today’s complementary metal-oxide semiconductor (CMOS) circuits owes much to a rich set of EDA tools. Superconducting electronic circuit design has unique requirements imposed by superconductivity that prevent repurposing all of the same EDA toolchain used for CMOS design and that require the development of additional tools. The existing EDA toolchain for SCE is currently incomplete and limited in capability [2, 5, 6]. IARPA is interested in learning the best path towards eliminating these deficiencies. Responses should focus primarily but not exclusively on applicability to the IARPA C3 program.

IARPA’s short-term goal is to significantly reduce design time, increase the reliability of designs, and enable the design of complex digital circuits with at least 1,000,000 Josephson junctions. The longer-term IARPA goal is to develop a fully integrated EDA toolchain for superconducting digital, analog and hybrid circuits, and bridge the gap between superconducting and CMOS design.

Questions:

• What relevant tools currently exist? What are the opportunities, challenges and limitations associated with adapting CMOS tools for superconducting use? What resources are required?
• Are there aspects of the CMOS development infrastructure other than tools that are important to the maturation of superconducting electronics design?
• What types of tools would be the most effective reducers of design time? What tools would provide the greatest reductions in design risk? Include estimates, if available.
• Are special tools needed for particular types of superconducting electronic circuits (e.g., RSFQ, RQL, analog, hybrid)? What tools are unique to superconducting circuits?

Desirable features:

• Applicable to all families of single flux quantum (SFQ) digital logic
• Work to clock speeds of 100 GHz or greater
• Compatible with an existing CMOS tool chain
• Able to optimize a design based on metrics such as circuit area, power, energy per operation, or speed

Full preparation instructions are available on iarpa.gov.

Source: IARPA